In order to fabricate integrated circuits, layers provided with different electrical properties are usually applied on a semiconductor substrate, e.g., a semiconductor wafer, and in each case patterned lithographically. A lithographic patterning step may include applying a photosensitive resist, exposing the latter with a desired structure for the relevant plane and developing it, and subsequently transferring the resist mask thus produced into the underlying layer in an etching step or using it for masking during an implantation.
In the field of semiconductor fabrication, use is made of photomasks or reticles on which the pattern is formed in order to form a pattern of structure elements on the semiconductor wafer by means of lithographic projection. During the lithographic projection, however, the lateral extent of the structure elements to be formed on the semiconductor wafer is restricted on account of a lower resolution limit predetermined by the projection system. The resolution limit is usually defined by the smallest distance that can still be separated between two structures formed in adjacent fashion on the surface of the semiconductor wafer. The resolution limit, also called structure resolution, depends on a number of factors. The resolution limit is proportional to the wavelength used during the exposure and inversely proportional to the aperture size of the lens system. However, it also depends for example on the type of illumination source of the projection system and other factors, the influence of which is usually described by means of a so-called k factor.
Large scale integrated circuits such as, by way of example, dynamic or non-volatile memories and also logic components are currently fabricated with circuit elements whose lateral extent reaches down to 70 nm. In the case of memory components, this applies, for example, to the very densely and periodically arranged pattern of narrow word or bit lines and, if appropriate, the corresponding contact connections or memory trenches.
The resolution limit of an optical projection system can be improved in a number of ways. Firstly, it is possible to reduce the exposure wavelength, but this leads to some problems particularly in the deep or extreme UV range. Secondly, it is also possible to use a projection system having a very high numerical aperture, as known, e.g., from immersion lithography. The resolution limit can likewise be reduced by using modern lithographic techniques in the case of the masks used for the exposure. This relates, e.g., to the field of phase masks that are used together with improved lithography techniques (litho-enhancement techniques). Phase masks of different types are used in this case, such as, e.g., alternating phase masks, halftone phase masks, tritone phase masks or chromeless phase masks. However, the techniques mentioned may also involve improvements in the imaging properties during the projection of the pattern on the mask, for example by the use of OPC structures (optical proximity correction) or other sublithographic elements.
All three contributions to improving the resolution are usually optimized in present-day process technology. Projection systems with light having the shortest possible wavelength with the highest possible numerical aperture are used for this purpose. In high-volume production technology it is often desirable to use already existing exposure devices for the next generation of semiconductor products as well, so that reducing the k factor and enlarging the numerical aperture play a critical part.
What is common to both procedures is that the masks used are in this case adapted to conditions prevailing in the exposure device, such as, e.g., type of exposure, but also to the required size of the process window. For this purpose, the pattern of the mask is usually optimized carefully in order to obtain a highest possible product yield. The masks used have to be free of defects, of course, these being monitored precisely prior to use in projection devices and possible defects, if possible, being repaired.
With the continuously increasing integration densities of integrated circuits, the requirement made of the positional accuracy of different layers with respect to one another also increases. The positional accuracy is influenced for example by the lithographic projection step, ever stricter tolerance limits with regard to the mutual orientation of the structure that is currently to be projected onto the substrate relative to the structures of preliminary planes having to be taken into account in order to ensure the functionality of the circuit.
In the high-volume fabrication of integrated circuits, the lateral extents of the individual structure elements of the patterns on each layer contribute to the product yield and are, therefore, subjected to a careful optimization process. In this case, it can happen, in particular, that it is found subsequently that a slight deviation from the previous dimension would result in an increased product yield. This is normally associated with the fact that the mask of the corresponding layer, which mask is carefully optimized and monitored as described above, can possibly no longer be used and has to be renewed. The above-described optimization method for the production of the mask and also the monitoring of the mask for freedom from defects in the latter thus likewise have to be carried out anew. This is associated with high costs and represents a known problem in industrial practice.